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AIC1384
DDR Termination Regulator
FEATURES
Source and Sink Current Capability Suspend To RAM Functionality Support DDR Requirements (1.25VTT) and DDR (0.9VTT)
DESCRIPTION
The AIC1384 linear regulator is designed to deliver 1.5A continuous current and up to 3A peak transient currents for termination of DDRSRAM. The AIC1384 contains a high-speed operational amplifier to supply superior load transient response. It also includes a VSENSE to provide excellent load regulation and VREF output as a reference for the chipset and DIMMs. The AIC1384 supply accurate VTT and VREF without external resistors that save PCB areas. The AIC1384 also features an active low shutdown pin that provides Suspend To RAM (STR) functionality. The VTT will remain high impedance when in shutdown, but VREF will keep active. The advantage of power saving can be obtained through low 150A (DDR ) quiescent current. Built in current limiting in source and sink mode, with thermal shutdown provide maximal protection to the AIC1384 against fault conditions.
Low Output Voltage Offset, 20mV High Accuracy Output Voltage at Full-Load Low External Component Count No external resistor required Current Limit protection Thermal Protection SOP-8 and SOP-8 Exposed Pad (Heat Sink) Package
APPLICATIONS
Mother board Graphic cards DDR and DDR termination voltage
TYPICAL APPLICATION CIRCUIT
VTT=1.25V Cout 22uF VIN=2.5V Cin 47uF
1 SD 2 3 VREF=1.25V 10nF 4
GND SD VSENSE VREF
VTT PVIN AVIN VDDQ
8 7 6 5 VDDQ=2.5V
AIC1384
Analog Integrations Corporation
Si-Soft Research Center 3A1, No.1, Li-Hsin Rd. I , Science Park , Hsinchu 300, Taiwan , R.O.C. TEL: 886-3-5772500 FAX: 886-3-5772510 www.analog.com.tw
DS-1384G-01 073108
1
AIC1384
ORDERING INFORMATION
AIC1384XXXX PACKING TYPE TR: TAPE & REEL TB: TUBE PACKAGING TYPE S: SOP-8 SH: SOP-8 Exposed Pad (Heat Sink) P: Lead Free Commercial G: Green Package Example: AIC1384PSTR In Lead Free SOP-8 Package & Taping & Reel Packing Type PIN CONFIGURATION
SOP-8 TOP VIEW GND 1 SD 2 VSENSE 3 VREF 4 SOP-8 Exposed Pad (Heat Sink) TOP VIEW GND 1 SD 2 VSENSE 3 VREF 4 (GND) 8 VTT 7 PVIN 6 AVIN 5 VDDQ 8 VTT 7 PVIN 6 AVIN 5 VDDQ
ABSOLUTE MAXIMUM RATINGS
PVIN, AVIN, VDDQ, SD , VSENSE, VREF, VTT, to GND Operating Temperature Range Junction Temperature Storage Temperature Range Lead Temperature (Soldering. 10 sec) Thermal Resistance Junction to Ambient, RJA (Assume no ambient airflow, no heatsink) SOP-8 SOP-8 Exposed Pad (Heat Sink) Thermal Resistance Junction to Case, RJC SOP-8 SOP-8 Exposed Pad (Heat Sink) 160C /W 60C /W 40C /W 16C /W 6.0V -40C ~ 85C 125C - 65C ~ 150C 260C
Absolute Maximum Ratings are those values beyond which the life of a device may be Impaired.
TEST CIRCUIT
Refer to TYPICAL APPLICATION CIRCUIT.
2
AIC1384
ELECTRICAL CHARACTERISTICS
(AVIN=2.5V, PVIN=VDDQ=1.8V / 2.5V, TA=25C, unless otherwise specified) (Note 1)
PARAMETER Input Voltage (DDR1/2) VDDQ = 1.7V VDDQ = 1.8V Reference Voltage VDDQ = 1.9V VDDQ = 2.3V VDDQ = 2.5V VDDQ = 2.7V IOUT = 0A, +0.9A, -0.9A VDDQ = 1.7V VDDQ = 1.8V VTT Output Voltage VDDQ = 1.9V IOUT = 0A, +1.5A, -1.5A VDDQ = 2.3V VDDQ = 2.5V VDDQ = 2.7V VTT Output Voltage Offset IOUT = 0A (for DDR I) (for DDR II) IOUT =+1.5A/ -1.5A IOUT =+0.9A/ -0.9A VDDQ = 2.5V, VREF Output Impendence IREF = -30A to +30A VDDQ = 1.8V, IREF = -20A to +20A Current Limit Quiescent Current VSENSE Input Current VTT Leakage Current in Shutdown
SD = 0V, VTT = 1.25V
CONDITIONS
SYMBOL AVIN PVIN VREF
MIN 2.2 1.6 0.83 0.88 0.93 1.127
TYP
MAX 5.5
UNITS V
2.5/1.8 0.85 0.90 0.95 1.15 1.25 1.35 0.85 0.90 0.95 1.15 1.25 1.35 0.87 0.92 0.97 1.177 1.277 1.377 0.89 0.94 0.99 1.181 1.281 1.381 20 25 40 40 2.5
V
VREF
1.227 1.327 0.81 0.86 0.91 1.116 1.216 1.316 -20 -25 -40 -40
V
VTT
V
VTT
V
VOS VOS
mV mV
VTT Output Voltage Offset IOUT = 0A
ZVREF 2.5 IIL IQ-AVIN ISD-AVIN ISENSE ILK-TT 13 10 3.0 1.6 320 500 150
k
PVIN = 2.5V PVIN = 1.8V IOUT = 0A
SD = 0V
A A nA A
3
AIC1384
ELECTRICAL CHARACTERISTICS (Continued)
PARAMETER Shutdown Leakage Current Shutdown Threshold Thermal Shutdown Temperature Thermal Shutdown Hysteresis
SD = 0V
CONDITIONS
SYMBOL ILK-SD VIH VIL TSD
MIN
TYP 2
MAX 5
UNITS A V C C
Output ON Output OFF
1.9 0.8 165 20
Note1: Specifications are production tested at TA=25C. Specifications over the -40C to 85C operating temperature range are assured by design, characterization and correlation with Statistical Quality Controls (SQC). Note 2: VOS is the voltage measurement, which is defined as VTT subtracted VREF. Note 3: Load regulation and Current Limit are measured at constant junction temperature, by using pulse test with a short ON time.
4
AIC1384
TYPICAL PERFORMANCE CHARACTERISTICS
112 108
IQ(uA)
IQ (uA)
290 280 270 260 250 240 230 220 210 200 2.0
104 100 96 92 88 2.0 2.5 3.0 3.5 4.0 AVIN (V) 4.5 5.0 5.5
2.5
3.0
4.0 3.5 AVIN (V)
4.5
5.0
5.5
Fig. 1 IQ vs. AVIN in Shutdown
4.0 3.5
1.32 1.30
Fig.2 IQ vs. AVIN
VSD (V)
3.0 2.5 2.0 1.5 1.0 0.5 2.0 2.5 3.0
VIH
VREF (V)
1.28 1.26
VIL
1.24
1.22 1.20
3.5 4.0 AVIN (V)
4.5
5.0
5.5
1.18 -30
-20
-10
0
10
20
30
IREF (uA)
Fig.3
3.0 2.5 2.0
AVIN vs. VSD
3.0 2.5 2.0
Fig.4 VREF vs. IREF
VREF (V)
VTT (V)
1.5 1.0 0.5 0.0
1.5 1.0 0.5
0
1
2
VDDQ (V)
3
4
5
6
0.0 0
1
2
3 VDDQ (V)
4
5
6
Fig.5
VREF vs. VDDQ
Fig.6
VTT vs. VDDQ
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AIC1384
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
1.4
2.6
OUTPUT CURRENT (A)
1.0 0.8 0.6 0.4 0.2 0.0
OUTPUT CURRENT (A)
1.2
2.4 2.2 2.0 1.8 1.6 1.4 1.2 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Fig.7
4.0 OUTPUT CURRENT (A) 3.6 3.4 3.2 3.0 2.8 2.6 2.4 3.0
Maximum Sourcing Current vs. AVIN (VDDQ=2.5V , PVIN=1.8V)
AVIN (V)
AVIN (V)
Fig.8
1.6
Maximum Sourcing Current vs AVIN (VDDQ=2.5V , PVIN=2.5V)
OUTPUT CURRENT (A)
3.5 4.0 4.5 AVIN (V) 5.0 5.5
3.8
1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Fig.9
4.0
Maximum Sourcing Current vs AVIN (VDDQ=2.5V , PVIN=3.3V)
Fig.10
Maximum Sourcing Current vs. AVIN (VDDQ=1.8V, PVIN =1.8V)
AVIN (V)
OUTPUT CURRENT (A)
3.8 3.6 3.4 3.2 3.0 2.8 3.0 3.5 4.0 4.5 5.0 5.5
Fig.11
Maximum Sourcing Current vs. AVIN (VDDQ=1.8V, PVIN =3.3V)
AVIN (V)
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AIC1384
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
3.4
3.0
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
3.2 3.0 2.8 2.6 2.4 2.2 2.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Fig.12
108
Maximum Sinking Current vs. AVIN (VDDQ=2.5V )
280 270
AVIN (V)
Fig.13
Maximum Sinking Current vs. AVIN (VDDQ=1.8V ) Q IN
o
AVIN (V)
104
0C
0C
o
260
100
25 C -40 C
IQ (uA)
o
o
25 C
o
250
-40 C 85 C 125 C
o o
o
IQ (uA)
96
85 C 125 C
o
o
240 230 220
92
88
210 200 2.0
84 2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
AVIN (V)
Fig14 IQ vs. AVIN in Shutdown
1.266 1.264 1.262 1.260 1.258 1.256 1.254
Fig15 IQ vs. AVIN
AVIN (V)
125 C -40 C
o o
o
VTT (V)
1.252 1.250 1.248 1.246 1.244 1.242 1.240 1.238 -100 -75 -50 -25 0 25 50 75 100
-40 C
125 C
o
IOUT (mA)
Fig16 VTT vs. IOUT
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AIC1384
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
Iout
Iout
VTT VTT
Cin: 47uF electrolytic capacitor Cout: 220uF electrolytic capacitor Cin: 47uF ceramic capacitor Cout: 22uF ceramic capacitor
Fig.17
-1.5A to +1.5A load transient
Fig.18
-1.5A to +1.5A load transient
Iout
Iout
VTT
Cin: 47uF electrolytic capacitor Cout: 220uF electrolytic capacitor
VTT
Cin: 47uF ceramic capacitor Cout: 22uF ceramic capacitor
Fig.19
-0.9A to +0.9A load transient
Fig.20
-0.9A to +0.9A load transient
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AIC1384
BLOCK DIAGRAM
SD VDDQ AVIN PVIN
50k VREF
+ 50k
+
VTT
VSENSE GND
PIN DESCRIPTION
Pin 1: GND Pin 2: SD - Ground. - Active low shutdown pin. Pin 7: PVIN Pin 6: AVIN - Analog input voltage to supply internal control circuitry. - Power input voltage to supply the rail voltage exclusively for the output stage used to create VTT. - Regulated VDDQ/2. output, equal to
Pin 3: VSENSE - Sense VTT to improve load regulation. Pin 4: VREF - Buffered output of internal reference voltage, equal to VDDQ/2.
Pin 8: VTT Heat Sink
Pin 5: VDDQ - Input voltage to internal reference voltage for regulating VTT.
- Recommended to Connect to GND.
9
AIC1384
APPLICATION INFORMATION
The AIC1384 linear termination regulator is designed to meet JEDEC requirements of DDRSDRAM (DDR / ). The VTT is able to deliver sinking and sourcing current while regulating the voltage equal to VDDQ/2. The output stage includes a sense function to maintain excellent load regulation to prevent shoot through. The power part has two distinct rails that split the internal analog circuitry from power output stage, which results in reducing internal power disspation. Series Stub Termination Logic (SSTL) was created to improve signal integrity of the data transmission across the memory bus. This termination scheme is necessary to prevent data error from signal reflections while transmitting at high frequencies encountered with DDR-SDRAM. The achievement of single parallel termination can be seen as below figure.
VIN VTT
increase at high PVIN. Connect AVIN and PVIN together with 2.5V is a good compromise in SSTL-2 applications. This reduces the need for bypassing two supply pins separately. For the safe operation of the system; AVIN must always exceed or equal to PVIN. VDDQ VDDQ is used to make internal reference voltage for regulating VTT. And VTT will track VDDQ/2 precisely because of internal resistor divider. For SSTL-2 application, connect VDDQ to the 2.5V rail directly at the DIMM instead of AVIN and PVIN to achieve that reference voltage tracks the DDR memory rails accurately without a voltage drop from power lines. VSENSE The sense pin is used to improve remote load regulation. The termination resistors in most motherboards connect to VTT with a long trace that will cause a significant voltage drop. The VSENSE pin can improve that a lower termination
RT ChipSet RS VREF
Memory
voltage at one end of the bus than the other by connecting it to the middle of the bus. If a long VSENSE trace is implemented close to the memory, noise pickup can be a problem in precise regulation of VTT. A small 0.1F ceramic capacitor can be used for filtering noise. VSENSE pin must still tie to VTT if remote load regulation is not used. VREF VREF provides the buffered output of the internal VDDQ/2 reference voltage. It can be used to support the reference voltage for the Northbridge chipset and memory. The VREF remains active during the shutdown state and thermal shutdown for the Suspend to RAM functionality. A bypass capacitor, located close to the VREF pin, can be used to improve performance. Ranging from
Between the chipset and memory are one RS series resistor and one RT termination resistor. Both RS and RT are 25 Ohms typically; they can be altered to scale the current requirements from the AIC1384. AVIN and PVIN AVIN and PVIN have the ability to work with separate supplies depending on the application. Higher PVIN will increase the maximum continuous output current resulting from output RDS-ON limitations at voltages close to VTT. Oppositely, the internal power dissipation will also
10
AIC1384
0.01F to 0.1F of ceramic capacitor is Thermal Dissipation The AIC1384 has a thermal-limiting circuitry, which is designed to protect the device against overload condition. For continuous load condition, maximum rating of junction temperature must not be exceeded. It is important to pay more attention in thermal resistance. It includes junction to case, junction to ambient. The maximum power dissipation of AIC1384 depends on the thermal resistance of its case and circuit board, the temperature difference between the die junction and ambient air, and the rate of airflow. The thermal resistance is greatly affected by the package used, the number of vias, the speed of airflow and the thickness of copper. When the IC mounting with good thermal conductivity is used, the junction temperature will be low even when large power dissipation applies. So the PCB mounting pad for GND pin of AIC1384 should provide maximum thermal conductivity to maintain low device temperature. The power dissipation across the device is P = IOUT (VIN-VOUT). The maximum power dissipation is: (T - TA ) PMAX = J-max R JA Where TJ-max is the maximum allowable junction temperature (125C), and TA is the ambient temperature suitable in application. Layout Considerations 1. Minimize high current ground loops. Place the ground of the device, the input capacitor, and the output capacitor together with short and wide connection. 2. Connect the bottom-side pad (available in SOP-8 Exposed Pad) to a large ground plane. Use as much copper as possible to decrease the thermal resistance of the device. 3. A buried layer may be used as a heat spreader if the large copper around the
recommended. VTT VTT is the regulated output that is used to terminate the bus resistor, which obtains the ability of sinking and sourcing current while regulating the output accurately to VDDQ/2. The AIC1384 is designed to deliver up to 3A peak transient currents with excellent transient response. The output capacitor should be large enough to prevent an excessive voltage drop if a transient is expected to last above the maximum continuous current rating for a significant amount of time. AIC1384 is able to provide large transient output currents, yet it can't handle for long durations under all conditions that results from the standard packages are not able to dissipate the heat of the internal power loss. If large currents are required for longer durations, ensure that the maximum junction temperature is not exceeded. Capacitor Selection The input capacitor of AIC1384 is required for improved performance during large load transients to prevent the input rail from dropping. 47F aluminum electrolytic capacitors or ceramic capacitor is recommended. If AVIN and PVIN are separated, the 47F capacitor should be placed as close as possible to the PVIN. And AVIN can bypass a 0.1uF ceramic capacitor to prevent excessive noise. 220F aluminum electrolytic capacitor is a recommendation for output capacitor to improve load transient response of VTT. And size above 22uF ceramic output capacitor is allowed to general used for obtain small profile. The value of ESR is determined by the acceptable maximum current spike and the output voltage droops.
11
AIC1384
device is not available. Use vias to lead the heat into the buried layer. 4. The input capacitor should be placed as close as possible to the PVIN pin. 5. A bypass capacitor, located close to the VREF pin, can be used to improve performance. Ranging from 0.01F to 0.1F of ceramic capacitor is recommended. 6. If long sense traces is used, the noise of VSENSE trace may occurs which from switching I/O signals. A 0.1uF ceramic capacitor connects to the VSENSE pin can be used to filter high frequency signal.
APPLICATION EXAMPLES
DDR Application
VTT=1.25V Cout 1 SD 2 3 VREF=1.25V 10nF 4 GND SD VSENSE VREF AIC1384 VTT PVIN AVIN VDDQ 8 7 6 5 VDDQ=2.5V Cin VIN=2.5V
All the input rails connect to 2.5V rail is recommend for the SSTL-2 termination scheme application. The circuitry completes an optimal power dissipation and component count.
VTT=1.25V Cout 1 SD 2 3 VREF=1.25V 10nF 4 GND SD VSENSE VREF AIC1384 VTT PVIN AVIN VDDQ 8 7 6 5 VDDQ=2.5V Cin VIN=3.3V
Connect the AIC1384 power rail to 3.3V to provide the maximum continuous output current if 1.8V and 2.5V rail are not available. Beware the junction temperature to exceed the maximum due to large current level. In this configuration AVIN will be limited to operation on the 3.3V or 5V rail results from PVIN can never exceed AVIN.
VTT=1.25V
AVIN and PVIN have the ability to work with separate supplies. PVIN can be operated on a lower 1.8V rail and the AVIN can be connected to a higher rail. Although this circuitry can obtain better efficiency, but the maximum continuous current is reduced due to the lower rail voltage. Increasing the output capacitance can also help for large load transients.
Cout
1
SD
GND
SD
VSENSE
VREF
AIC1384
VTT
8
2
3
PVIN
7
1.8V
2.2~5.5V
AVIN
6
VREF=1.25V
4
VDDQ
5
VDDQ=2.5V
0.1uF
Cin
10nF
12
AIC1384
DDR Application
VTT=0.9V
Cout
1
SD
GND
SD
VSENSE
VREF
AIC1384
VTT
8
The circuit is recommended for DDR-II applications.
1.8V
2
3
PVIN
7
The output stage is connected to the 1.8V rail and the AVIN pin can be connected to either a 3.3V or 5V rail.
AVIN
6
2.2~5.5V
VREF=0.9V
4
VDDQ
5
VDDQ=1.8V
0.1uF
Cin
10nF
VTT=0.9V
Connect the power rail to 3.3V to provide a higher continuous output current if 1.8V rail is not available. Careful with the junction temperature that may exceed the maximum due to the thermal dissipation increases with lower VTT output voltages. In this configuration PVIN will be limited to operation on the 3.3V rail.
Cout
1
SD
GND
SD
VSENSE
VREF
AIC1384
VTT
8
2
3
PVIN
7
VIN=3.3V
AVIN
6
VREF=0.9V
4
VDDQ
5
VDDQ=1.8V
Cin
10nF
Level Shifting Application
VTT Cout 1 R1 2 3 R2 4 GND SD VSENSE VREF AIC1384 VTT PVIN AVIN VDDQ 8 7 6 5 VDDQ Cin VIN
The AIC1384 is available to scale the output to any voltage required. One method is to level shift the output above the internal reference voltage of VDDQ/2 by using two resistors from the VTT to the VSENSE. The correct voltage at VTT is VTT = VDDQ/2 (1 + R1/R2)
VTT Cout 1 R1 2 3 R2 4 GND SD VSENSE VREF AIC1384 VTT PVIN AVIN VDDQ 8 7 6 5 VDDQ Cin VIN
Another method is to level shift the output below the internal reference voltage of VDDQ/2 by using two resistors from the VSENSE and VDDQ. The correct voltage at VTT is VTT = VDDQ/2 (1 - R1/R2)
13
AIC1384
PHYSICAL DIMENSIONS
SOP- 8
D
S Y M B O L
(unit: mm)
SOP-8 MILLIMETERS MIN. 1.35 0.10 0.33 0.19 4.80 3.80 1.27 BSC 5.80 0.25 0.40 0 6.20 0.50 1.27 8 MAX. 1.75 0.25 0.51 0.25 5.00 4.00
A
H
E
A1 B C D
h X 45
E
e
A
A
SEE VIEW B
e H h L
A
B A1
WITH PLATING BASE METAL SECTION A-A
0.25
L
VIEW B
GAUGE PLANE SEATING PLANE
Note: 1. Refer to JEDEC MS-012AA. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side . 3. Dimension "E" does not include inter-lead flash or protrusions. 4. Controlling dimension is millimeter, converted inch dimensions are not necessarily exact.
C
14
AIC1384
SOP- 8 Exposed Pad (Heat Sink)
D
S Y M B O L
E1
SOP-8 Exposed Pad(Heat Sink) MILLIMETERS MIN. 1.35 0.00 0.31 0.17 4.80 3.80 1.27 BSC 5.80 0.25 0.40 0 6.20 0.50 1.27 8 MAX. 1.75 0.15 0.51 0.25 5.00 4.00
D1
H
E
EXPOSED THERMAL PAD(Heat Sink) (BOTTOM CENTER OF PACKAGE)
A A1 B C D
SEE VIEW B
h X 45
e
A
A
E e H h
A
L
B A1
WITH PLATING BASE METAL SECTION A-A
q
D1
C
1.5 1.0
3.5 2.55
E1
0.25 L
VIEW B
GAUGE PLANE SEATING PLANE
Note : 1. Refer to JEDEC MS-012E. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side . 3. Dimension "E" does not include inter-lead flash or protrusions. 4. Controlling dimension is millimeter, converted inch dimensions are not necessarily exact.
Note:
Information provided by AIC is believed to be accurate and reliable. However, we cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in an AIC product; nor for any infringement of patents or other rights of third parties that may result from its use. We reserve the right to change the circuitry and specifications without notice. Life Support Policy: AIC does not authorize any AIC product for use in life support devices and/or systems. Life support devices or systems are devices or systems which, (I) are intended for surgical implant into the body or (ii) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
15

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